Nader Bagherzadeh, Ph.D.
Professor of Computer Engineering, Department of Electrical Engineering and Computer Science at the University of California, Irvine.
Nader Bagherzadeh is a professor of computer engineering at UC Irvine, where he previously served as department chair (1998–2003). His research spans computer architecture, reconfigurable computing, VLSI chip design, Network-on-Chip (NoC), 3D ICs, embedded systems, sensor networks, memory systems, and computer graphics. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE, 2014) for contributions to coarse-grained reconfigurable processor architectures and has authored more than 400 peer-reviewed publications.
Consulting Focus
NBTEK partners with research teams and technology organizations seeking breakthrough silicon systems. Professor Bagherzadeh brings a rare blend of academic depth and industry experience from his time at AT&T Bell Labs (1980–1984), providing actionable guidance from early architecture trade studies through tape-out readiness.
- System-on-Chip (SoC) architecture for high-performance and low-power designs.
- Network-on-Chip and 3D IC communication fabrics, including wired and wireless NoC.
- Reconfigurable computing and coarse-grained accelerator architectures.
- Embedded and memory systems optimization for real-time workloads.
- Hardware/software co-design for graphics, signal processing, and AI pipelines.
- Fault-tolerant and energy-aware VLSI design strategies.
Education
- Ph.D., Computer Engineering, University of Texas at Austin (1987)
- M.S., Electrical Engineering, University of Texas at Austin (1979)
- B.S., Electrical Engineering, University of Texas at Austin (1977)
Research Leadership
Professor Bagherzadeh leads research in scalable SoC platforms based on Network-on-Chip architectures that connect hundreds of cores on a single die. His group advances low-power routers, mapping and scheduling algorithms, fault-tolerant NoC designs, and 3D IC integration using Through-Silicon Vias (TSVs) and wireless interconnects.
Selected Publications & Impact
Representative papers relevant to advanced computing systems, reconfigurable hardware, and embedded design. Citation counts reflect broad research influence.
- MorphoSys: An integrated reconfigurable system for data-parallel and computation-intensive applications
- Design and implementation of the MorphoSys reconfigurable computing processor
- Power-aware scheduling under timing constraints for mission-critical embedded systems
- A framework for reconfigurable computing: Task scheduling and context management
- A scalable register file architecture for dynamically scheduled processors
- Performance study of a multithreaded superscalar microprocessor
- Optimal Ring Embedding in Hypercubes with Faulty Links
- Efficient Mitchell's approximate log multipliers for convolutional neural networks
- A wireless network-on-chip design for multicore platforms
- The effects of approximate multiplication on convolutional neural networks
Notable Works
- MorphoSys: an integrated reconfigurable system for data-parallel applications.
- Design and implementation of the MorphoSys reconfigurable computing processor.
- Power-aware scheduling for mission-critical embedded systems.
- Optimal ring embedding in hypercubes with faulty links.
- Scalable register file architecture for dynamically scheduled processors.
- A framework for reconfigurable computing: task scheduling and context management.
- Performance study of a multithreaded superscalar microprocessor.
Awards & Recognition
- IEEE Fellow (2014) for contributions to coarse-grained reconfigurable processors.
- Khwarizmi International Award, 27th Session (2014).
- Best Paper Award, IEEE Transactions on VLSI Design (2002).
- Best Paper Award, Asia and South Pacific Design Automation Conference (2002).